 IF S3C44B0_TEST_PLATFORM>0
top_of_stack	EQU		0x0C007FFC	;S3C44B0
 ELSE
top_of_stack	EQU		0x00007FFC	;cust
 ENDIF


		IMPORT	c_main
;		IMPORT  s3c44bx_init
		IMPORT	VectorTable

; --- Amount of memory (in bytes) allocated for stacks

Len_FIQ_Stack    EQU     256
Len_IRQ_Stack    EQU     256
Len_ABT_Stack    EQU     0
Len_UND_Stack    EQU     0
Len_SVC_Stack    EQU     1024
Len_USR_Stack    EQU     1024
Len_SYS_Stack    EQU     0

Offset_FIQ_Stack         EQU     0
Offset_IRQ_Stack         EQU     Offset_FIQ_Stack + Len_FIQ_Stack
Offset_ABT_Stack         EQU     Offset_IRQ_Stack + Len_IRQ_Stack
Offset_UND_Stack         EQU     Offset_ABT_Stack + Len_ABT_Stack
Offset_SVC_Stack         EQU     Offset_UND_Stack + Len_UND_Stack
Offset_USR_Stack         EQU     Offset_SVC_Stack + Len_SVC_Stack
Offset_SYS_Stack         EQU     Offset_USR_Stack + Len_SYS_Stack


; Add lengths >0 for FIQ_Stack, ABT_Stack, UND_Stack if you need them.
; Offsets will be loaded as immediate values.
; Offsets must be 8 byte aligned.


; --- Standard definitions of mode bits and interrupt (I & F) flags in PSRs
Mode_USR        EQU     0x10
Mode_FIQ        EQU     0x11
Mode_IRQ        EQU     0x12
Mode_SVC        EQU     0x13
Mode_ABT        EQU     0x17
Mode_UND        EQU     0x1B
Mode_SYS        EQU     0x1F ; available on ARM Arch 4 and later

I_Bit           EQU     0x80 ; when I bit is set, IRQ is disabled
F_Bit           EQU     0x40 ; when F bit is set, FIQ is disabled
T_Bit			EQU		0x20 ; when T bit is set, Thumb instruction

		EXPORT	Mode_USR
		EXPORT	Mode_FIQ
		EXPORT	Mode_IRQ
		EXPORT	Mode_SVC
		EXPORT	Mode_ABT
		EXPORT	Mode_UND
		EXPORT	Mode_SYS
		
		EXPORT	I_Bit
		EXPORT	F_Bit
		EXPORT	T_Bit

;----------------------------------------------------------------------------;
        AREA    start, CODE, READONLY
; The code area containing c_main
; The section of code to HiReset has been copied over from the DEMON code 
; level0.s & level0_h.s
;----------------------------------------------------------------------------;
        AREA    start, CODE, READONLY

		ENTRY                           ; Define the image entry point.

	    B		Reset_Handler			; Reset point location 0x00000000
	    LDR		pc, =VectorTable+0x08	; undefined
	    LDR		pc, =VectorTable+0x10	; SWI
	    LDR		pc, =VectorTable+0x18	; Prefetch
	    LDR		pc, =VectorTable+0x20	; Abort
	    LDR		pc, =VectorTable+0x28	; undefined
	    LDR		pc, =VectorTable+0x30	; IRQ
	    LDR		pc, =VectorTable+0x38	; FIQ


__main
;
; This is the initial entry point to the image.
; Have to establish a stack for C
; No arguments are passed to c_main from an embedded application,
; so argc and argv are set up to 0
; Reset sets the processor to SVC32 mode interrups dissabled


		EXPORT Reset_Handler
Reset_Handler
; --- Initialize stack pointer registers
        LDR     r0, =top_of_stack

  IF 0<Len_FIQ_Stack
        MSR     CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit ; No interrupts
        SUB     sp, r0, #Offset_FIQ_Stack

;		LDR		r8, =|TIMER_BASE_ADDR|+0xE0		;timer3 raw status
;		LDR		r9, =|TIMER_BASE_ADDR|+0xE0
;		LDR		r10, =int_counter_fiq
  ENDIF

  IF 0<Len_IRQ_Stack
        MSR     CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit ; No interrupts
        SUB     sp, r0, #Offset_IRQ_Stack
  ENDIF

  IF 0<Len_ABT_Stack
        MSR     CPSR_c,  #Mode_ABT:OR:I_Bit:OR:F_Bit ; No interrupts
        SUB     sp, r0, #Offset_ABT_Stack
  ENDIF

  IF 0<Len_UND_Stack
        MSR     CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit ; No interrupts
        SUB     sp, r0, #Offset_UND_Stack
  ENDIF

  IF 0<Len_SYS_Stack
 		MSR		CPSR_c, #Mode_SYS:OR:I_Bit:OR:F_Bit ; No interrupts
 		SUB		sp, r0, #Offset_SYS_Stack
  ENDIF
  
        MSR     CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit ; No interrupts
        SUB     sp, r0, #Offset_SVC_Stack

;	BL		s3c44bx_init

	BL		c_var_init

; --- Now enter the C code
    B      c_main


	IMPORT	|Image$$RO$$Limit|
	IMPORT	|Image$$RW$$Base|
	IMPORT	|Image$$RW$$Limit|
	EXPORT	c_var_init
c_var_init
; CODE TO INITIALIZE GLOBAL VARIABLES IN 'C'
	LDR		r8, =|Image$$RO$$Limit|
	LDR		r9, =|Image$$RW$$Base|
	LDR		r10,=|Image$$RW$$Limit|

	CMP		r8, r9
	BXEQ	lr
	
loop_init_cvar
	LDMIA	r8!, {r0-r7}
	STMIA	r9!, {r0-r7}
;	LDR		r0, [r8], #4
;	STR		r0, [r9], #4
	CMP		r9, r10
	BCC		loop_init_cvar

	BX		lr

	EXPORT enable_irq
	EXPORT disable_irq

disable_irq
;unsigned long disable_irq(void)
	MRS r0, CPSR
	TST r0, #0x80
	ORREQ r1, r0, #0x80
	MSREQ CPSR_c, r1
	MOV	pc, lr

enable_irq
;void enable_irq(unsigned long I_BIT)
	TST r0, #0x80
	MOVNE pc, lr
	MRS r0, CPSR
	TST r0, #0x80
	BICNE r0, r0, #0x80
	MSRNE CPSR_c, r0
	MOV pc,	lr



	EXPORT fifo_br16
;void fifo_burst_read16(unsigned short *entry, unsigned short *buf, unsigned length cnt)
fifo_br16
	stmdb	r13!, {r2-r11}
	add		r2, r1, r2, lsl #0x1

fifo_br16_loop
	cmp		r2,   r1
	ldmhiia	r0,  {r4-r11}
	add		r4, r4, r6, lsl #0x10
	add		r5, r8, r10,lsl #0x10
	stmhiia	r1!, {r4-r5}
	bhi		fifo_br16_loop
	
	ldmia	r13!, {r2-r11}
	mov		pc, lr

        END

